1. Field of the Invention
The invention relates to the field of electrical interconnection within microelectronics fabrications. More particularly, the invention relates to the field of patterned self-aligned silicide layers for electrical interconnection within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications employ layers of microelectronics materials formed over substrates and into patterns to embody the active devices and other components which are interconnected to form the circuitry of the microelectronics fabrication. The formation of low resistance electrical interconnections is an important factor in achieving the desired circuit performance in such microelectronics fabrications. Increased density of components employed within microelectronics fabrications has resulted in closer spacing between the structures which constitute the components. This places even greater emphasis on the need for such characteristics as low resistance electrical interconnections, low resistance electrical contacts and compatibility with other microelectronics processes.
Various conductor materials have been employed in patterned microelectronics layers in microelectronics devices and circuits. Although intrinsically low electrical resistance is generally a high priority requirement, other factors are also of significance. Thus, although aluminum and aluminum alloys are widely employed as electrical interconnection materials in microelectronics, the relatively low melting point and chemical and metallurgical reactivity of these materials may not serve the purpose of the design or fabrication scheme. Materials such as tungsten, polycrystalline silicon, silicide compounds and other refractory metal compounds are conductive materials which may be conveniently formed in patterned layers, and which may offer advantages in some cases due to their high melting temperatures.
Electrical connections may be formed employing patterned layers of metal silicide compounds, which are conductor materials with relatively low electrical resistance and high melting temperatures. When such metal silicide conductor materials are employed within microelectronics fabrications in such a fashion as to form self-aligned silicide interconnections and contacts, such self-aligned silicide interconnections are referred to as salicide interconnections and contacts. Such self-alignment character may be achieved, for example, by etching contact regions through a dielectric layer to an underlying polycrystalline silicon conductor layer and depositing thereupon an appropriate metal layer. Subsequent treatment such by, for example, rapid thermal heating brings about formation of the silicide compound between the polysilicon and metal layers in the contact regions only, whereafter the superfluous metal and polysilicon may be removed. Such salicide layers are commonly employed as gate electrodes for field effect transistor (FET) devices. Such salicide gate electrodes are generally provided with adjacent dielectric spacer layers.
Among the requirements for fabrication of complex, high-density microelectronics devices and circuits such as memory cell arrays is the need to form local interconnections or crossovers, which are electrical interconnections bridging between adjacent contact regions separated by insulating or isolation regions. For example, an array of memory cells may require a personalization interconnection scheme which is a series of unique local inter-cell interconnections or crossovers to give that particular memory array its personality or unique feature, such as a read-only memory (ROM). The possibility of non-symmetrical patterns and the likelihood of relatively sparsely populated features in such a cross-over pattern may lead to difficulties in subsequent processing of the microelectronics fabrication, particularly with respect to maintaining planarization of the resulting upper surfaces of the fabrication. This is particularly likely to cause problems when conductor materials which are very hard and brittle, such as tungsten, are employed because of their high temperature capability.
Because of their more advantageous physical properties, salicide interconnection layers have become increasingly widely employed in microelectronics fabrications. The selfaligning feature and inherently low electrical resistance of many metal silicide materials are especially important as dimensions and design ground rules have continued to diminish. However, the employment of salicide interconnections and contacts to form cross-over electrical contacts is not without problems. For example, the employment of conventional microelectronics fabrication methods to form patterned layers of insulating material, polysilicon, metal silicide and the like and to form low resistance interconnections may be expensive and result in defects, low yields and reliability problems.
It is thus towards the goal of forming within a microelectronics fabrication a low resistance local electrical interconnection or cross-over for bridging over insulating regions which is compatible with further processing that the present invention is generally directed.
Methods and materials are known in the art of microelectronics fabrication for formation of cross-over bridging electrical contacts over insulating regions to two or more contact regions with low electrical resistance, high reliability and compatibility with microelectronics fabrication processes.
For example, Holloway et al., in U.S. Pat. No 4,657,628, disclose a method fort forming patterned local interconnects to source and drain regions of different FET devices. The method employs the formation of titanium silicide in the source and drain device contact regions, and interconnecting them with a patterned titanium nitride conductor layer.
Further, Tang et al., in U.S. Pat. No. 5,010,032, disclose a method for formation of both p+and n+gates in a CMOS device wherein there is an interconnection of the devices employing a patterned titanium nitride layer. The interconnection is made by placing the titanium nitride layer in contact with titanium silicide contact regions formed upon the sources, gates and drains of the FETs in the CMOS device.
Still further, Kuo, in U.S. Pat. No. 6,083,847, discloses a local interconnection method for FET gate electrodes. The method employs the selective removal of the dielectric sidewall spacer of a polysilicon gate electrode and formation of a metal silicide layer after deposition of the metal on the exposed gate electrode and substrate contact areas.
Yet still further, Dawson et al., in U.S. Pat. No. 6,096,639, disclose a method for forming a local interconnect (LI) structure to selected regions of a semiconductor device. The method employs the formation of silicide regions where electrical contact is to be made, and then depositing an insulating layer and a transition or refractory metal layer which is then patterned to form the local interconnect to the silicide regions.
Further still, Lin et al., in U.S. Pat. No. 6,100,191, disclose a method for forming self-aligned silicide layers on a substrate. The method employs a deposition of a non-conformal silicon layer selectively on the substrate followed by a deposition of a refractory metal layer thereupon. A thermal annealing step then converts the superposed layers to a self-aligned silicide layer.
Finally, Manning, in U.S. Pat. No. 6,117,761, discloses a method for forming self-aligned silicide interconnection to polysilicon layers separated by non-conducting gaps. The method employs the deposition of a metal layer over a contact opening in a substrate exposing first and second silicon layers, followed by formation of a silicon layer over the metal layer. A thermal sintering step forms a silicon-rich silicide region over the first and second silicon layers, thus bridging the gap.
Desirable in the art of microelectronics fabrication are further novel methods for the formation of cross-over electrical interconnections bridging over insulating regions and employing low resistance, high temperature conductor materials. It is towards these goals that the present invention is more specifically directed.
A first object of the present invention is to provide a method for forming within a substrate employed within a microelectronics fabrication an electrical cross-over interconnection bridging over an insulating region.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the cross-over interconnection is formed employing a low resistance conductor material.
A third object of the present invention is to provide a method in accord with the first and second objects of the present invention, where the electrical crossover is formed from a high temperature material compatible with conventional microelectronics fabrication methods.
A fourth object of the present invention is to provide in accord with the first object of the present invention, the second object of the present invention and/or the third object of the present invention, a structure for an electrical crossover interconnection bridging between conductive regions separated by an insulating region.
A fifth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention, the third object of the present invention and/or the fourth object of the present invention, where the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming within a substrate employed within a microelectronics fabrication an electrical cross-over interconnection to two or more contact regions bridging an insulating region between the contact regions. To practice the invention, there is provided a substrate with electrical contact regions. There is formed over the substrate a thin layer formed of silicon oxide dielectric material. There is formed over the silicon oxide dielectric layer a polycrystalline silicon layer. There is then etched employing a conventional photoresist etch mask layer the electrical cross-over pattern into the polysilicon and silicon oxide dielectric layers. There is then stripped the photoresist etch mask layer. There is then etched away a small portion of the silicon oxide dielectric layer, leaving a narrow peripheral gap between the overhanging polysilicon layer and the contact region in the underlying substrate. There is then formed a layer of metal over the substrate which upon thermal treatment forms a metal silicide over the surface of the polysilicon and within the narrow gap between the polysilicon and the substrate, resulting in the formation of an electrical connection in the peripheral gap between the polysilicon layer and the substrate contact regions, and hence a self-aligned silicide or salicide cross-over electrical interconnection.
The present invention provides a method for forming within a substrate employed within a microelectronics fabrication a structure which affords an electrical cross-over interconnection bridging interconnection between contact regions separated by an insulating region. The present invention may be employed to form cross-over electrical connections within substrates employed within microelectronics fabrications including but not limited to integrated circuit microelectronics fabrications, charge coupled device microelectronics fabrications, solar cell microelectronics fabrications, optoelectronics microelectronics fabrications, ceramic substrate microelectronics fabrications and flat panel display microelectronics fabrications.
The method of the present invention employs materials and methods which are known in the art of microelectronics fabrication, but in a novel order and sequence to bring about a novel structure. Therefore the method of the present invention is readily commercially implemented.